작성일 : 18-07-17 04:09
[논문 Accepted-TCASII] A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit with an Input Slew-rate Tolerant Selective Transition Detector
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글쓴이 :
김민규
조회 : 1,439
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논문 제목: A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit with an Input Slew-rate Tolerant Selective Transition Detector
논문 저자: Dae-Hyun Kwon, Minkyu Kim, Sung-Geun Kim, and Woo-Young Choi
저널명: Transactions on Circuits and Systems II
도움 주신 분들과 교수님의 지도에 감사드립니다.
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